CMOS technology has evolved such that the computer market has rapidly opened to a wide range of consumers. Today multi-media requires at least a 16 MB and preferably even a 32 MB memory, which increases the relative cost of the memory system within a computer. In the near future, it is likely that 64 MB and 128 MB computers will become commonplace, which suggests a potential demand for 256 Mb DRAMs (Dynamic Random Access Memory) and beyond. Still in the development stage, DRAMs in the Gigabit range are already under way, which necessitate the introduction of new techniques that guarantee the repairability of the product notwithstanding the added complexity of the design and manufacture of such memory devices. Despite the huge array size and lithographic difficulties that ensue, it is more important than ever to increase the chip yield. Process engineers are continuously attempting to reduce and, ultimately, eliminate mask defects. Faults that inevitably remain in the chip are generally overcome using special circuit designs, and, more specifically, redundancy replacement.
Conventional redundancy configurations typically employ a Fixed Domain Redundancy Replacement (FDRR) architecture, wherein redundancy elements are used to replace defective elements within a fixed size domain for each row and column redundancy.
A typical redundancy architecture commonly used for low density DRAMs is shown in FIG. 1a. Therein are depicted a plurality of spares that are used for replacing defective elements within the domain, and which are appended to each sub-array comprising the memory. Each redundancy unit (RU) includes a small number of redundancy elements (RE), (e.g., two REs per RU are illustrated herein), which are used to repair existing faults (labeled X) within the corresponding sub-array. This arrangement, labeled intra-block replacement, expands the redundancy area overhead as the number of sub-arrays increases for high density memories, since each sub-array encompasses a domain for replacement purposes, and the domains in different sub-arrays are mutually exclusive of each other. This requires at least one or, preferably, two RUs in each sub-array. Thus, the efficiency of the RUs is rather poor in view of its inflexibility. This reduces the chip yield substantially when faults are clustered in a given sub-array. The above-mentioned concept is embodied in a configuration described in an article by T. Kirihata et al., entitled "A 14 ns 4 Mb DRAM with 300 mW Active Power", published in the IEEE Journal of Solid State Circuits, Vol. 27, No. 9, pp. 1222-1228, September 1992.
A second redundancy architecture, known as flexible redundancy replacement configuration is shown in FIG. 1b, wherein a memory is depicted having a single array as a large domain of RUs to selectively replace failing elements anywhere in the memory. In this configuration, REs within the RU repair faults (labeled X) located in any sub-array within the memory. The advantage of this arrangement over the previously described intra-block replacement is that one section, namely, a redundancy array, having a certain number of RUs may advantageously be used to service any number of sub-arrays forming the memory. This translates into a significant saving of real estate over the previous scheme, although it requires a substantial amount of added control circuitry to properly service all the sub-arrays forming the memory.
More details regarding the above configurations and the various trade-off may be found in an article by T. Kirihata et al., "Fault-Tolerant Designs for 256 Mb DRAMs", published in the IEEE Journal of Solid-state Circuits, Vol. 31, No. 4, pp. 588-566, April 1996; in an article by T. Sugibayashi et al., "A 30 ns 256 Mb DRAM with Multi-divided Array Structure", published in the IEEE Journal of Solid State Circuits, Vol. 28, No. 11, pp. 1092-1098, November 1993; and in an article by H. L. Kalter et al., "A 50 ns 16 Mb DRAM with a 10 ns Data Rate and On-Chip ECC", published in the IEEE Journal of Solid State Circuits, Vol. 25, No. 5, pp. 1118-1128, October 1990.
Regardless of the intra-block replacement arrangement shown in FIG. 1a and the flexible redundancy replacement configuration illustrated in FIG. 1b, they all use wordlines or bitlines as line redundancy. Therefore, the repairability is limited to relatively small faults, such as single bit faults, wordline faults or bitline faults. Although the flexible redundancy replacement can repair somewhat larger faults, a line redundancy replacement, even with its added flexibility, finds it difficult to repair block faults when a memory block contains in excess of 1 Mb cells, as for instance, in a 256 Mb DRAM, that renders the memory device totally inoperative.
Accordingly, a third redundancy architecture has been advanced, known as a block redundancy replacement configuration and shown in FIG. 1c, wherein a block redundancy completely replaces a defective memory block. A memory block is defined as an entire memory region supported by wordline drivers and sense amplifiers. By way of example, and with reference to FIG. 1d, a 256 Mb DRAM chip (100) is shown containing sixteen 16 Mb units (105). Each unit (105) consists of sixteen 1 Mb block (110), each with a 1 Mb array (120), a sense amplifier block SA (130), and a row decoder block RDEC (140). Each 16 Mb unit (105) is also provided with one 1 Mb block redundancy (115). The advantage of this arrangement over previously described ones related to line redundancy replacement is that a block fault (i.e., 110-i, i being an integer larger or equal to 0), typically caused by the wordline driver or by a sense amplifier, can be repaired by replacing it with a block redundancy (115). A power-bus fault can also be repaired by isolating the defective block from the power-bus by replacing it with a redundancy block. As the DRAM density increases, the probability of block faults also occurring increases, an obvious yield detractor for 256 Mb DRAMs and beyond. A fuller description of a block redundancy replacement is described in an article by G. Kitsukawa et al., entitled "256-Mb DRAM Circuit Technologies for File Applications", published in the IEEE Journal of Solid State Circuits, Vol. 28, pp. 1105-1113, November 1993.
In spite of its advantages, Kitsukawa's block redundancy replacement suffers in at least one aspect, namely, it imposes a substantial penalty for its implementation. The size of a redundancy block must be equal or larger than the array block, otherwise its repairability is poor since the majority of block faults are caused by a defective wordline driver, sense amplifier, or power bus. The area penalty of the block redundancy is over 6% for the 256 Mb DRAM, assuming a conventional implementation having one 1 Mb block redundancy for each 16 Mb unit (intra-unit block redundancy). Designing redundancy blocks in a peripheral region (shared block redundancy) allows a redundancy block to be shared among others. However, added column circuitry for the redundancy block is required, which is oftentimes difficult to implement. It also increases the complexity of the wiring for the flexible block replacement, resulting in lower speeds. A detailed embodiment of shared block redundancy is discussed in an article by J. H. Yoo et al., entitled "A 32-Bank 1 Gb DRAM with 1 Gb/s Bandwidth", and published in the IEEE Journal of Solid State Circuits, Vol. 31, pp. 1635-1644, November 1996. Using column circuitry in both the normal block and the redundancy block significantly reduces the design overhead, as was the case for Kitsukawa's block redundancy replacement. Regardless, in Kitsukawa's intra-unit block redundancy and Yoo's shared block redundancy, the defective redundancy block (110-2) cannot be used even if it only contains a single fault (160). The probability of having a fault within a redundancy block is significant, reducing the effectiveness of the block redundancy. Introducing line redundancy repair means for the block redundancy element can overcome the problem; however, it requires a two-step redundancy programming, in which a redundancy block is first repaired and then having the block redundancy repair the defective block. The detailed embodiment of a two step block redundancy with variable size redundancy architecture is discussed in the article by T. Kirihata et. al., entitled "Variable Size Redundancy Replacement Architecture to Make a Memory Fault-Tolerant", filed in an U.S. patent application, Ser. No. 08/825,949 (Attorney docket FI9-97-002), in April 1997.
Other redundancy replacement configurations, including some related to the categories listed above, are described in the following references:
U.S. Pat. No. 5,491,664 to Phelan, issued Feb. 13, 1996, describes the implementation of a flexible redundancy memory block elements in a divided array architecture scheme. This configuration has both, the memory and redundancy memory blocks, coupled to a read bus to allow the redundancy memory in one memory sub-array to be shared by a second sub-array.
U.S. Pat. No. 5,475,648 to Fujiwara, issued Dec. 12, 1995, in which a memory having a redundancy configuration is described such that when an appropriate address signal agrees with the address of a defective cell, a spare cell provided by the redundant configuration is activated to replace the failing one.
U.S. Pat. No. 5,461,587 to Seung-Cheol Oh, issued Oct. 24, 1995, in which a row redundancy circuit is used in conjunction with two other spare row decoders, wherein by a judicious use of fuse boxes, signals generated by a row redundancy control circuit, make it possible to replace failing rows with spare ones.
U.S. Pat. No. 5,459,690 to Rieger at al., issued Oct. 17, 1995, describes a memory with a redundant arrangement that, in the presence of normal wordlines servicing defective memory cells, enables faulty memory cells to be replaced with redundant cells.
U.S. Pat. No. 5,430,679 to Hiltebeitel et al., issued Jul. 4, 1995, describes a fuse download system for programming decoders for redundancy purposes. The fuse sets can be dynamically assigned to the redundant decoders, allowing a multi-dimensional assignment of faulty rows/columns within the memory.
U.S. Pat. No. 5,295,101 to Stephens, Jr. et al., issued Mar. 15, 1994, describes a two level redundancy arrangement for replacing faulty sub-arrays with appropriate redundancy elements.
Whereas the prior art and previous discussions have been described mainly in terms of DRAMs, practitioners of the art will fully appreciate that the above configurations and/or architectures are equally applicable to other types of memories, such as SRAMs, ROMs, EPROMs, EEPROMs, Flash RAMs, CAMs, and the like.